1. Field of the Invention
The present invention relates to a power semiconductor device used for controlling a large power, particularly, to an element having a super junction structure and used in, for example, a vertical power MOSFET, SBD, MPS diode, SIT, JFET or IGBT.
2. Description of the Related Art
In a vertical power MOSFET, which is one of power semiconductor elements, the on-resistance is greatly dependent on the electrical resistance of the conductive layer (drift layer) portion. The dopant concentration determining the electrical resistance of the drift layer cannot be increased to exceed a limit in accordance with the breakdown voltage of the pn junction formed between the base layer and the drift layer. Therefore, there is a trade-off relationship between the breakdown voltage of the element and the on-resistance. It is important to the low consumption power element to improve the trade-off relationship. The trade-off has a limit determined by the material of the element. In order to achieve a low on-resistance element exceeding the existing power element, it is necessary to exceed the limit noted above.
Known as an example of the MOSFET effective for overcoming the problem noted above is an MOSFET in which a resurf structure, which is called a super junction structure, is buried in the drift layer.
FIG. 13A is a cross sectional view schematically showing the construction of a vertical power MOSFET having a resurf structure buried therein. In the MOSFET shown in the drawing, an n+-type drain layer 2 is formed on one surface of an n-type drift layer 3, and a drain electrode 1 is formed on the n+-type drain layer 2. Also, a plurality of p-type base layers 5 are selectively formed on the other surface of the n-type drift layer 3, and an n+-type source layer 6 is selectively formed on the surface of each of the p-type base layers 5.
A gate insulating film 8 is formed to cover the surfaces of the n+-type source layer 6, the p-type base layer 5, the n-type drift layer 3, the adjacent p-type base layer 5 and the n+-type source layer 6 formed within the p-type base layer 5, and a gate electrode 9 is formed on the gate insulating film 8. Also, a source electrode 7 is formed on the p-type base layer 5 in a manner to surround the gate electrode 9 with the gate insulating film 8 interposed therebetween. The source electrode 7 thus formed is connected to the surfaces of the n+-type source layer 6 and the p-type base layer 5.
A p-type resurf layer 4 connected to the p-type base layer 5 is formed within the n-type drift layer 3 positioned between the p-type base layer 5 and the drain electrode 1. In this case, formed is a vertical resurf structure in which the p-type resurf layer 4 and the n-type drift layer 3 are alternately repeated in the lateral direction. It is possible to increase the impurity concentration in the n-type drift layer 3 by narrowing the clearance of the resurf (cell width) so as to lower the on-resistance.
FIG. 13B shows the impurity concentration profile in the vertical direction in the n-type drift layer 3 and the p-type resurf layer 4 in the vertical power MOSFET shown in FIG. 13A. The n-type drift layer 3 and the p-type resurf layer 4 are equal to each other in the impurity concentration and has a prescribed impurity concentration profile in the vertical direction.
What is important in manufacturing the MOSFET of the construction described above is how to design the super junction structure. To be more specific, the impurity concentration in the n-type drift layer 3 and the p-type resurf layer 4 constitutes an important factor for determining the breakdown voltage and the on-resistance.
In principle, the impurity concentration can be made equivalently zero by making the impurity concentration in the n-type drift layer 3 equal to that in the p-type resurf layer 4 so as to obtain a high breakdown voltage. Therefore, it is possible to make the impurity concentration in the n-type drift layer 3 higher than the impurity concentration in the drift layer in the conventional MOSFET while retaining the breakdown voltage so as to realize a low on-resistance exceeding the limit of the material.
However, in manufacturing the MOSFET, it is difficult to make the amount of the impurity in the n-type drift layer 3 perfectly equal to that in the p-type resurf layer 4 because of the nonuniformity in the process so as to deteriorate the breakdown voltage.
Such being the situation, it is necessary to design the element in view of the deterioration of the breakdown voltage caused by the nonuniformity in the manufacturing process. In this case, for lowering the on-resistance, it is effective to increase the impurity concentration in the n-type drift layer 3. It should be noted in this connection that the process margin relative to the breakdown voltage is determined by the unbalance amount, i.e., the difference in the amount of the impurity between the n-type drift layer 3 and the p-type resurf layer 4. In other words, even if the impurity concentration in the n-type drift layer 3 is increased, the unbalance amount that can be taken as a process margin remains unchanged.
It follows that, if the impurity concentration in the n-type drift layer 3 is increased, the ratio of the allowable unbalance amount to the amount of the impurity in the n-type drift layer 3 is diminished so as to diminish the process margin. On the other hand, in order to ensure a wide process margin, it is necessary to lower the impurity concentration in the n-type drift layer 3, with the result that the on-resistance is increased.
Incidentally, Japanese Patent Disclosure (Kokai) No. 2001-244472 shows in FIG. 1 a semiconductor device that permits increasing the allowable on-current and suppressing the output capacity and the on-resistance while satisfying the required breakdown voltage. In the semiconductor device disclosed in this prior art, an n++-type drain region and a p+-type well region are formed apart from each other in an n-type semiconductor layer of an SOI structure. Also, an n++-type source region is formed within the p+-type well region, and an n-type drift region is formed between the n++-type drain region and the p+-type well region. Further, the impurity concentration within the n-type drift region is distributed such that the impurity concentration is lowered away from the n++-type drain region in each of the lateral direction and the vertical direction of the n-type semiconductor layer.
Japanese Patent Disclosure No. 2001-313391 discloses in FIG. 1 a super junction semiconductor device that permits suppressing the injection of hot carriers into an insulating film and that does not impair the characteristics and reliability of the element active region. The super junction semiconductor device disclosed in this prior art comprises a drain-drift section of a parallel pn junction structure. In this prior art, a p-type breakdown voltage limiter region having a high impurity concentration is formed in that portion of the p-type partition region which forms the well bottom surface of the p-type base region.
U.S. Pat. No. 6,291,856 shows in FIGS. 3 and 4 an MOSFET of a super junction structure, in which the amount of an impurity in the drift layer is defined.
Further, Japanese Patent Disclosure No. 2000-286417 shows in FIG. 1 a lateral MOSFET of a multi-resurf structure. It is taught that a low on-resistance and a high breakdown voltage can be achieved simultaneously in this prior art.
Still further, a power semiconductor element of a super junction structure having a high breakdown voltage and a low on-resistance is disclosed in “Lateral Unbalanced Super junction (USJ/3D-RESURF for High Breakdown Voltage on SOI” by R. Ng, et al, Proceedings of 2001 International Symposium on Power Semiconductor Devices & ICs, Osaka, pp. 395-398. It is taught that the power semiconductor layer of a super junction structure can be achieved by employing a lateral structure in the semiconductor layer of an SOI structure.
As described above, in the conventional vertical power MOSFET, the reduction of the on-resistance is contradictory to the requirement for the expansion of the process margin in respect of the amount of the impurity relative to the breakdown voltage. The difficulty is coped with by setting the impurity concentration in the n-type drift layer 3 at an appropriate value in designing the semiconductor device.